With ever increasing speed and complexity of electronic circuits, it is desirable that the noise, specifically the phase noise performance of clock signals for these electronic circuits does not degrade. Hence, the degradation of the phase alignment due to aging, temperature, mechanical stress, and other factors need to be addressed and remedied. This issue is typically addressed through complicated calibration processes, which although may provide initial calibration, they do not dynamically compensate for drift, aging, etc. Rather, the present methods periodically and manually perform the re-calibration.
More particularly, conventional clock distribution circuits manually adjust delay elements as part of the calibration or re-calibration. These circuits are typically open loop and thus are susceptible to temperature, mechanical stress, and aging that cause the circuit to lose calibration. Also, the existing schemes are not integrated. Moreover, the ability to integrate a large number of timing adjustments on the same integrated circuit (IC) provides additional reduction of skew.
For example, antenna arrays are becoming increasingly larger over time. The number of elements in the future antenna arrays will most likely be in the thousands. These arrays will require the distribution of high frequency, low phase noise clocks to receiver/exciter electronics, with the ability to adjust for phase delays between clock signals as a result of the difference in distance for the individual clocks to the individual receiver/exciter elements in the array. This must be done without degrading the phase noise and thermal noise floor of the reference clock signal (i.e., without adding any additional jitter to the clock signal). Additionally, it is important to be able to dynamically adjust for clock signal drift due to aging, temperature, mechanical stress, and other factors without the need for periodic re-calibration.
Therefore, there is a need for a digitally controlled clock distribution architecture or circuit, which can be used for the large scale, affordable sub-picosecond synchronization of distributed processors, radios, antenna arrays, data samplers, and the like operating at tens of Giga Hertz (GHz) clock frequencies to hundreds or thousands of nodes (clock loads).